1. Field of the Invention
The present invention relates to an image sensor and a related layout method thereof capable of reducing noises, and more particularly, to an image sensor and a related layout method of blocking light illumination on voltage floating nodes in correlation double sampling (CDS) circuits to avoid noise occurrences by properly arranging metal lines utilized for providing electrical connections for each node in the CDS circuits.
2. Description of the Prior Art
As the development of electronic products such as digital cameras and mobile phones progresses, the demand for image sensors increases accordingly. In general, image sensors are divided into two main categories: charge coupled device (CCD) sensors and CMOS image sensors (CIS). Primarily, CMOS image sensors have certain advantages of low operating voltages, low power consumption, and an ability for random access. Furthermore, CMOS image sensors are currently capable of integration with the semiconductor fabrication process. Based on those benefits, the application of CMOS image sensors has increased significantly.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional CMOS image sensor 10. The CMOS image sensor 10 includes a pixel array 11, a correlation double sampling (CDS) circuit array 12, a row decoder 13, a column decoder 14 and an analog to digital converter 15. The pixel array 11 includes pixel units P11-Pmn arranged in a matrix form. Each of the pixel units P11-Pmn has a light-sensing region and a peripheral circuit region (not shown in FIG. 1.) The light-sensing region is utilized for sensing incident light and accumulating photo charges that are generated due to the incident light. The peripheral circuit region is utilized for properly outputting signals generated by the light-sensing region according to control signals of the row decoder 13 and the column decoder 14. The CDS circuit array 12 is arranged below the pixel array 11, and includes CDS circuits 120_1-120_n. Each CDS circuit 120 is individually coupled to a corresponding column of the pixel array 11, and is utilized for reading signals outputted from the corresponding column. The analog to digital converter 15 is arranged on a side of the pixel array 11, and is utilized for performing signal processing such as analog-to-digital conversion for signals outputted by the CDS circuits 120_1-120_n, successively.
As known by those skilled in the art, the peripheral circuit region of each pixel unit is formed by transistors, and thus photo charge signals outputted from each pixel unit may have fixed pattern noises (FPN) caused by transistor parameter differences between each pixel unit. Therefore, in the conventional CMOS image sensor, the CDS circuit array 12 is utilized for double sampling data signals (i.e. the photo charge signals) and reset signals outputted from each pixel unit, and the analog to digital converter 15 is further utilized for computing differences between the data signals and the reset signals, so as to prevent images being generated from having the fixed pattern noises induced by parameter differences of the transistors.
Please refer to FIG. 2. FIG. 2 is a schematic diagram of a CDS circuit 120 in FIG. 1. The CDS circuit 120 includes a switch 121, a sampling capacitor 122 and a buffer 123. The switch 121 is utilized for switching data signals or reset signals received from the pixel array 11 according to the control signal outputted by the column decoder 14. The sampling capacitor 122 is coupled to the switch 121, and is utilized for storing the data signals or the reset signals received through the switch 121. The buffer 123 is coupled to a node A, and is utilized for outputting a voltage of the node A to the analog to digital converter 15 according to the control signal outputted by the column decoder 14. Thus, after the CDS circuit 120 completes the reception of the data signals or the reset signals, the switch 120 is turned off for allowing the analog to digital converter 15 to successively read out voltages kept in the sampling capacitor 122 of each CDS circuit 120.
At this time, the voltages kept in the CDS circuit 120 cannot be interfered with by external noises before being read out by the analog to digital converter 15. However, the node A is possessed of a voltage floating property when the switch 121 is turned off, so the node A is often labeled as “a floating node” by those skilled in the art.
However, photo-electric effects are easily generated when light illuminating on the floating node A, so as to change the voltages kept by the sampling capacitor 122 and further induce noises. Besides, depending on locations of each CDS circuit 120 in the CDS circuit array 12, angles and amplitudes of light illuminating on each CDS circuit 120 are different as well as extents to which they are interfered with by the noises. In this case, the use of the CDS circuits is not effective for reducing image noises, which further influences performance of the CMOS image sensor.
In the prior art, photoresist or metal blocks are generally utilized for blocking light illumination on the peripheral circuit regions of the CMOS image sensor to further reduce noise interferences caused by optical energy. However, the photoresist cannot effectively insulate light incidence, and the use of metal blocks is greatly limited due to cost concern and circuit dimensions.